Certain embodiments of the inventive concept relate to Peripheral Component Interconnect (PCI) devices, and more particularly, to PCI devices enabling a PCI host to continuously transmit data via a PCI bus to a memory of the PCI device without additional interaction between the PCI host and the PCI device. Other embodiments of the inventive concept relate to PCI systems including this type of PCI device.
PCI is a local bus standard commonly used to connect the Central Processing Unit (CPU) of a computer system with various peripheral components. PCI express (PCIe), another bus standard that is widely used in contemporary digital systems, defines a high-speed, serial data, computer expansion bus that is intended to largely replace the PCI and PCI extended (PCI-X) bus standards.
Conventionally, a PCI host is allowed to access only a limited memory area according to the size of a base address register (BAR) included in a PCI device. Since a resource allocation error occurs in a PCI BAR when the size of the PCI BAR is set large, the PCI host is allowed to access only limited memory area allocated in small size. In addition, when the PCI host transmits data larger than the PCI BAR size, the PCI host is required to transmit a first part of the data in a size defined by the PCI BAR size, and then transmit a second (e.g., a remaining) part of the data to the PCI device after receiving and processing a transmission completion message associated with the first part and received from the PCI device.
Consequently, some additional interaction between the PCI device and PCI host is required whenever the PCI host transmits an amount of data to the PCI device that is larger than the size of the PCI BAR. Accordingly, system performance related to the transmission of data between the PCI host and PCI device deteriorates.